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Simulating Fault Induced Delayed Voltage Recovery

asked 2019-09-13 21:45:51 -0500

bikiran1991 gravatar image

I am trying to simulate Fault Induced Delayed Voltage Recovery by motor stalling. I see that the family of ACMTBL models have that capability. Does anyone know where i can find sample parameters for this model, or for any induction motor model with stalling capability.

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answered 2019-09-16 11:20:11 -0500

acd1 gravatar image

In my experience (in the USA) the typical model we use for loads which can simulate FIDVR is the CMLDxx composite load model family. If you are dead-set on ACMTBL then I won't be able to help, but if you can use the CMLD model, then I can provide some typical parameters. See the model following my post.

You'll need to update the bus number and load ID. You can adjust the fractions of each motor type at CONS J+18 through J+22. The Motor D stalling parameters begin at CON J+103.

There is an absolute ton of material out there on these CMLD models, and I highly recommend reading some of it to ensure you are using the model as intended.

<bus number> 'USRLOD' <load ID> 'CMLDBLU1'        12    1    0  132   27  146   48

     -1.0000       0.0000      0.40000E-01  0.40000E-01  0.75000    
     0.80000E-01   1.0000       1.0000       1.0000      0.90000    
      1.1000      0.62500E-02   1.0250       1.0400       30.000    
      5.0000       0.0000       0.0000      0.64000E-01  0.94000E-01
     0.50000E-01  0.23300      0.18800       1.0000      0.70000    
     0.50000      -1.0000       2.0000      0.19200       1.0000    
     0.80800       0.0000       2.0000     -0.50001       1.0000    
      1.5000      -1.0000    

      3.0000      0.75000      0.40000E-01   1.8000      0.12000    
     0.10400      0.95000E-01  0.21000E-02  0.10000       0.0000    
     0.70000      0.20000E-01  0.20000       1.0000       99999.    
     0.50000      0.20000E-01  0.70000      0.70000      0.10000    

      3.0000      0.75000      0.30000E-01   1.8000      0.19000    
     0.14000      0.20000      0.26000E-02  0.50000       2.0000    
     0.60000      0.20000E-01  0.20000      0.75000      0.50000E-01
     0.50000      0.20000E-01  0.30000      0.65000      0.50000E-01

      3.0000      0.75000      0.30000E-01   1.8000      0.19000    
     0.14000      0.20000      0.26000E-02  0.10000       2.0000    
     0.65000      0.20000E-01  0.20000       1.0000       9999.0    
     0.50000      0.20000E-01  0.30000      0.65000      0.10000    
      9999.0       0.30000       0.20000E-01   0.50000E-01
      1.0000       0.98000       0.60000       0.10000    
     0.10000        0.0000        0.0000        1.0000    
      6.0000        2.0000        12.000        3.2000    
      11.000        2.5000       0.86000       0.20000    
     0.95000        1.0000       -3.3000       0.50000    
     0.40000       0.60000       0.50000        15.000    
     0.70000        1.9000       0.10000       0.60000    
     0.20000E-01    1.0000        9999.0      /
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thanks! i am not dead set on the ACMTBL model, just looking for a load model with which i can simulate FIDVR. Will try it and see. By tons of literature, do you mean the stuff in PAGV2? Can you recommend other sources?

bikiran1991 gravatar imagebikiran1991 ( 2019-09-16 12:49:14 -0500 )edit

Here is a paper that NERC's Load Modeling Task Force put out: https://www.nerc.com/comm/PC/LoadModelingTaskForceDL/Dynamic%20Load%20Modeling%20Tech%20Ref%202016-11-14%20-%20FINAL.PDF A quick google of CMLD model also showed a bunch of other material. Hope that helps!

acd1 gravatar imageacd1 ( 2019-09-16 13:56:56 -0500 )edit

Thanks a lot!

bikiran1991 gravatar imagebikiran1991 ( 2019-09-16 14:49:09 -0500 )edit

One note/correction on the model I posted - for FIDVR studies you will need to enable stalling by lowering the J+97 CON (Tstall) from 9999 to something much smaller. The NERC recommendation is about 0.033.

acd1 gravatar imageacd1 ( 2019-09-16 15:17:23 -0500 )edit

The model works fine if i implement it a single load bus. However, when i do this for all load buses in the IEEE 39 case, i get convergence errors right at initialization, with all the exciters and governors out of limits. Timestep : 0.00008333, acceleration factor: 0.3. Any advice on this?

bikiran1991 gravatar imagebikiran1991 ( 2019-09-19 11:09:08 -0500 )edit

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Asked: 2019-09-13 21:45:51 -0500

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Last updated: Sep 16 '19