in a dynamic simulation: Is there any way that you can apply a SLG found in one end, open the same end at 6 cycles, fault still on and open the other end of the line at a delayed clearing time of 9 cycles? then clear the fault by opening the line. the question is how to do it, without the use of a user-created dummy bus; but rather what is available in PSSE calculating the fault with the short circuit module. thanks in advance
Hi, what about the distspcbfault_2 function? It looks like it has breaker opening capabilities but I am not sure if it would suit your application exactly.
Chapter 11.7 of the PSSE 33.9 PAGV1 gives some example of it's use in a SLG fault with single pole tripping without using dummy busses to open the near and far end breakers using different clearing times.
Solving this without a dummy bus is a little tricky, even PSS/E uses a dummy bus to calculate open end line faults in short circuit module!
If you still want to do it without a dummy bus you might do something like this:
Clear the fault.
The tricky thing is to calculate the fault shunt in step 3 above.
EDIT: Perform the simulation in the following way by using a dummy bus:
Do the following.
1: Do LTAP and place the dummy bus at From bus line end.
2: Start simulation, run to x seconds and add LG fault at Dummy bus.
3: Simulate for 6 cycles.
4: Clear fault.
5: Trip line from Dummy to From bus.
6: Apply LG fault at Dummy bus (new calculation of equivalent shunt with line open-end will be done)
6: Run for 3 cycles.
7: Disconnect Dummy bus.
8: Run to x seconds.
Step 3 cannot be done using what is available in PSSE as "Dynamics/ Apply Disturbance". The goal was to use "apply unbalance fault at Bus..." so it can be automated. PSSE adds a dummy Bus. PSSE adds a dummy Bus but it is not available to the user (cannot trip B to dummy)
You cannot perform this simulation with Dynamics/Apply Disturbance. You have to add the dummy bus before the simulation and first perform the necessary SCMU calculations (before and after opening the line breaker at line end) and take note of the Positive sequence equivalent fault admittance.
Asked: 2016-11-20 17:06:30 -0500
Seen: 1,578 times
Last updated: Nov 24 '16
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