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Standard simulations parameter values for integration step size is 1/4 of a cycle (60 Hz), acceleration factor set to 1. Verify that during case conversion, TSYL activity converged in 1 or 2 iterations. Select minimum but necessary set of channels. Send output of process to a log file (or to null device) instead of the default screen. Try running the simulation outside the PSSe GUI, using python and PSSe API. These settings will give you a baseline simulation time. Deviations from these settings may render longer simulation times.
For a dynamic run, 3-5 sec total simulation time is fast. If you have to do multiple runs (>100) consider parallel processing. Search this forum for more related posting.
