Revision history [back]
 | 1 | initial version |
The dyr data format looks ok. I would add a time delay to the first UF stage. I assume there is load at bus 40003.
did you check the log during initialization for errors related to load at bus 40003 or if the contingency took out such load?
| | 2 | No.2 Revision |
The dyr data format looks ok. I would add a time delay to the first UF stage. I assume there is load at bus 40003.
did you check the log during initialization for errors related to load at bus 40003 or if the contingency took out such load?
Check your PSSe version. Suggest to upgrade to latest version v.33.12.2,
• UVUFBLU1 - Fixed an issue in the load shed logic pertaining to frequency relay part of the load relay model. This issue was preventing load being shed by the frequency relay. Additionally, this issue would have resulted in the model VAR location of another model getting changed.
